| Design technology co-optimization for a robust 10nm Metal1 solution for Logic design and SRAM B Vandewalle, B Chava, S Sakhare, J Ryckaert, M Dusa Design-Process-Technology Co-optimization for Manufacturability VIII 9053 …, 2014 | 94 | 2014 |
| High-aspect-ratio ruthenium lines for buried power rail A Gupta, S Kundu, L Teugels, J Bommels, C Adelmann, N Heylen, ... 2018 IEEE International Interconnect Technology Conference (IITC), 4-6, 2018 | 61 | 2018 |
| Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery J Ryckaert, A Gupta, A Jourdain, B Chava, G Van der Plas, D Verkest, ... 2019 Electron Devices Technology and Manufacturing Conference (EDTM), 50-52, 2019 | 42 | 2019 |
| Standard cell design in N7: EUV vs. immersion B Chava, D Rio, Y Sherazi, D Trivkovic, W Gillijns, P Debacker, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427, 110-118, 2015 | 41 | 2015 |
| DTCO at N7 and beyond: patterning and electrical compromises and opportunities J Ryckaert, P Raghavan, P Schuddinck, HB Trong, A Mallik, SS Sakhare, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427, 101-108, 2015 | 37 | 2015 |
| DTCO exploration for efficient standard cell power rails B Chava, J Ryckaert, L Mattii, SMY Sherazi, P Debacker, A Spessot, ... Design-Process-Technology Co-optimization for Manufacturability XII 10588, 89-94, 2018 | 35 | 2018 |
| Power Delivery Network (PDN) Modeling for Backside-PDN Configurations With Buried Power Rails and TSVs MO Hossen, B Chava, G Van der Plas, E Beyne, MS Bakir IEEE Transactions on Electron Devices 67 (1), 11-17, 2019 | 34 | 2019 |
| SRAM with buried power distribution to improve write margin and performance in advanced technology nodes SM Salahuddin, KA Shaik, A Gupta, B Chava, M Gupta, P Weckx, ... IEEE electron device letters 40 (8), 1261-1264, 2019 | 34 | 2019 |
| Low track height standard cell design in iN7 using scaling boosters SMY Sherazi, C Jha, D Rodopoulos, P Debacker, B Chava, L Matti, ... Design-Process-Technology Co-optimization for Manufacturability XI 10148 …, 2017 | 32 | 2017 |
| Design technology co-optimization for N10 J Ryckaert, P Raghavan, R Baert, MG Bardon, M Dusa, A Mallik, ... Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-8, 2014 | 31 | 2014 |
| Impact of a SADP flow on the design and process for N10/N7 metal layers W Gillijns, SMY Sherazi, D Trivkovic, B Chava, B Vandewalle, V Gerousis, ... Design-Process-Technology Co-optimization for Manufacturability IX 9427, 71-79, 2015 | 29 | 2015 |
| Architectural strategies in standard-cell design for the 7 nm and beyond technology node SMY Sherazi, B Chava, P Debacker, MG Bardon, P Schuddinck, F Firouzi, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 15 (1), 013507-013507, 2016 | 25 | 2016 |
| Backside power delivery as a scaling knob for future systems B Chava, KA Shaik, A Jourdain, S Guissi, P Weckx, J Ryckaert, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 14 | 2019 |
| TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes A Mallik, P Zuber, TT Liu, B Chava, B Ballal, PR Del Bario, R Baert, ... Proceedings of the 50th Annual Design Automation Conference, 1-6, 2013 | 14 | 2013 |
| System design technology co-optimization for 3D integration at< 5nm nodes SC Song, G Nallapati, I Khan, N Nikfar, B Yan, M Miranda, B Lim, ... 2021 IEEE International Electron Devices Meeting (IEDM), 22.3. 1-22.3. 4, 2021 | 8 | 2021 |
| Metal stack optimization for low-power and high-density for N7-N5 P Raghavan, F Firouzi, L Matti, P Debacker, R Baert, SMY Sherazi, ... Design-Process-Technology Co-optimization for Manufacturability X 9781, 231-238, 2016 | 7 | 2016 |
| FPGA implementation and resource utilization for QRD-RLS systolic array for signal processing applications KR Santha, BC Chava, K Bragadishwaran, K Chandru TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009 | 7 | 2009 |
| Integrated circuits (ICs) employing front side (FS) back end-of-line (BEOL)(FS-BEOL) input/output (I/O) routing and back side (BS) BEOL (BS-BEOL) power routing for current flow … B Chava, SS Song, MY Shariff US Patent 11,270,991, 2022 | 4 | 2022 |
| Post place and route design-technology co-optimization for scaling at single-digit nodes with constant ground rules L Mattii, D Milojevic, P Debacker, M Berekovic, SMY Sherazi, B Chava, ... Journal of Micro/Nanolithography, MEMS, and MOEMS 17 (1), 013503-013503, 2018 | 4 | 2018 |
| Stacked die integrated with package voltage regulators B Chava, SS Song, ROY Abinash, J Kim US Patent 11,515,289, 2022 | 2 | 2022 |
