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Hechen Wang
Hechen Wang
Research Scientist, Intel Labs
Verified email at intel.com - Homepage
Title
Cited by
Cited by
Year
An 802.11a/b/g/n Digital Fractional- PLL With Automatic TDC Linearity Calibration for Spur Cancellation
D Liao, H Wang, FF Dai, Y Xu, R Berenguer, SM Hermoso
IEEE Journal of Solid-State Circuits 52 (5), 1210-1220, 2017
592017
An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation
D Liao, H Wang, FF Dai, Y Xu, R Berenguer
2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 134-137, 2016
592016
A Reconfigurable Vernier Time-to-Digital Converter With 2-D Spiral Comparator Array and Second-Order Linearization
H Wang, FF Dai, H Wang
IEEE Journal of Solid-State Circuits 53 (3), 738-749, 2018
452018
A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology
H Wang, FF Dai
ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 143-146, 2017
372017
A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference
H Wang, R Liu, R Dorrance, D Dasalukunte, D Lake, B Carlton
IEEE Journal of Solid-State Circuits, 2023
322023
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference
H Wang, R Liu, R Dorrance, D Dasalukunte, X Liu, D Lake, B Carlton, ...
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
282022
A bidirectional lens-free digital-bits-in/-out 0.57mm2 terahertz nano-radio in CMOS with 49.3mW Peak power consumption supporting 50cm Internet-of-Things communication
T Chi, H Wang, MY Huang, FF Dai, H Wang
Custom Integrated Circuits Conference (CICC), 2018 IEEE, 1-4, 2018
272018
A bidirectional lens-free digital-bits-in/-out 0.57mm2 Terahertz nano-radio in CMOS with 49.3mW peak power consumption supporting 50cm Internet-of-Things …
T Chi, H Wang, MY Huang, FF Dai, H Wang
Custom Integrated Circuits Conference (CICC), 2017 IEEE, 1-4, 2017
272017
A 280MS/s 12b SAR-Assisted Hybrid ADC with Time Domain Sub-Range Quantizer in 45nm CMOS
Z Su, H Wang, H Zhao, Z Chen, Y Wang, FF Dai
2019 IEEE Custom Integrated Circuits Conference (CICC), pp. 1-4, 2019
242019
A 330μW 1.25ps 400fs-INL vernier time-to-digital converter with 2D reconfigurable spiral arbiter array and 2nd-order ΔΣ linearization
H Wang, FF Dai, H Wang
2017 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2017
142017
Sub-Sampling Direct RF-to-Digital Converter With 1024-APSK Modulation for High Throughput Polar Receiver
H Wang, FF Dai, Z Su, Y Wang
IEEE Journal of Solid-State Circuits 55 (4), 1064-1076, 2020
132020
Energy Efficient BNN Accelerator using CiM and a Time-Interleaved Hadamard Digital GRNG in 22nm CMOS
R Dorrance, D Dasalukunte, H Wang, R Liu, B Carlton
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022
42022
An 8-bit 80-MS/s fully self-timed SAR ADC with 3/2 interleaved comparators and high-order PVT stabilized HBT bandgap reference
Z Su, H Wang, H Zhao, X Liu, FF Dai
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2019
42019
Radio frequency (RF) to digital polar data converter and time-to-digital converter based time domain signal processing receiver
F Dai, H Wang
US Patent 10,785,075, 2018
42018
A wide tuning triple-band frequency generator MMIC in 0.18 μm SiGe BiCMOS technology
H Wang, F Zhao, FF Dai, G Niu, B Wilamowski, J Fu, W Zhou, Y Wang
2014 IEEE Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), 199-202, 2014
42014
A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation
H Wang, Z Su, H Zhao, Y Wang, FF Dai
2019 Symposium on VLSI Circuits, pp. C82-C83, 2019
32019
Sram-based in-memory computing macro using analog computation scheme
R Liu, H Wang, R Dorrance, D Dasalukunte
US Patent App. 17/816,442, 2022
22022
Bayesian neural network and methods and apparatus to operate the same
H Wang, R Dorrance, D Dasalukunte, DIG Aguirre
US Patent App. 17/075,527, 2021
22021
A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs
R Dorrance, A Belogolovy, H Wang, X Zhang
2020 30th International Conference on Field-Programmable Logic and …, 2020
22020
Analog chip paves the way for sustainable AI
H Wang
Nature 620 (7975), 731-732, 2023
12023
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