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Dr.Navneet Kaur
Dr.Navneet Kaur
Assistant Professor,GNDEC Ludhiana
Verified email at gndec.ac.in
Title
Cited by
Cited by
Year
Comparative simulation analysis of process parameter variations in 20 nm triangular FinFET
S Shukla, SS Gill, N Kaur, HS Jatana, V Nehru
Active and passive electronic components 2017, 2017
192017
Design and optimization of novel shaped FinFET
N Kaur, M Rattan, SS Gill
Arabian Journal for Science and Engineering 44, 3101-3116, 2019
172019
Performance analysis of rectangular and trapezoidal TG bulk FinFETs for 20 nm gate length
A Gaurav, SS Gill, N Kaur
2015 Annual IEEE India Conference (INDICON), 1-5, 2015
152015
A novel low leakage and high density 5T CMOS SRAM Cell in 45nm technology
R Gupta, SS Gill, N Kaur
2014 Recent Advances in Engineering and Computational Sciences (RAECS), 1-6, 2014
132014
Impact of gate oxide thickness and aspect ratio of fin height and fin width on nanoscale tapered FinFETs
N Kaur, M Rattan, SS Gill
2016 IEEE International Conference on Recent Trends in Electronics …, 2016
112016
Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA
A Gaurav, SS Gill, N Kaur, M Rattan
2016 20th International Symposium on VLSI Design and Test (VDAT), 1-5, 2016
102016
Performance optimization of Broadwell-Y shaped transistor using artificial neural network and Moth-flame optimization technique
N Kaur, M Rattan, S Gill
Majlesi Journal of Electrical Engineering 12 (1), 61-69, 2018
92018
Performance evaluation of various hybrid modulation techniques transmitted by EDFA in radio-over-fibre communication
AS Kang, S Bhatia, N Kaur, K Singh
Journal of Information and Telecommunication 4 (3), 295-313, 2020
72020
Optimization of dual-K gate dielectric and dual gate heterojunction SOI FinFET at 14 nm gate length
SK Aujla, N Kaur
IETE Journal of Research 68 (1), 658-666, 2022
62022
Artificial magnetic conductor for miniaturized antenna applications-A Review
C Jain, N Kaur, G Kaur
International Journal of Emerging Technology and Advanced Engineering (ISSN …, 2012
32012
Marine predators algorithm for performance optimization of nanoscale FinFET
N Kaur, M Rattan, SS Gill, G Kaur, GK Walia, K Rajvir.
Materials Today: Proceedings, 2022
22022
Influence of Fin Dimensions on Performance of Nanoscale Rectzoidal Bulk Fin Shaped Field Effect Transistor
N Kaur, M Rattan, SS Gill
Journal of Nanoelectronics and Optoelectronics 14 (3), 389-399, 2019
22019
Performance analysis of 20 nm pentagonal and trapezoidal nanowire transistor with Si and Ge channel
SS Gill, J Kaushik, N Kaur
International Journal of Circuits and Electronics 1, 174-184, 2016
22016
Performance Evaluation of Junctionless FinFET using Spacer Engineering at 15 nm Gate Length
N Kaur, SS Gill, P Kaur
Silicon 14 (16), 10989-11000, 2022
12022
Comparison of Electrical Characteristics of Si Homojunction and SiGe Heterojunction 14 nm SOI FinFET
SK Aujla, N Kaur
Journal of The Institution of Engineers (India): Series B 103 (4), 1061-1067, 2022
12022
Temperature Dependence of Multi-fin FinFET for Bulk and SOI Substrate at 20 nm Channel Length
S Singh, SS Gill, N Kaur
Sustainable Development Through Engineering Innovations: Select Proceedings …, 2021
12021
Modelling and mitigation of single-event upset in CMOS voltage-controlled oscillator
S Shukla, SS Gill, HS Jatana, V Nehru, N Kaur
Sādhanā 43, 1-10, 2018
12018
Performance Analysis of Junction Less Accumulation Mode (JAM) Bulk FinFETs Using Dual-K Spacers at 15nm Gate Length
P Kaur, SS Gill, N Kaur
2018 2nd International Conference on Trends in Electronics and Informatics …, 2018
12018
Impact of si/sige heterojunction on dual gate and dual gate dielectric material SOI finfet
SK Aujla, N Kaur
2017 International Conference on Computing Methodologies and Communication …, 2017
12017
Analysis of influence of temperature on 20nm triangular bulk FinFET
S Singh, SS Gill, N Kaur
2016 IEEE International Conference on Recent Trends in Electronics …, 2016
12016
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