Prof. (Dr.) Priyadarsan Patra

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Elias KougianosProfessor of Electrical Engineering, University of North TexasVerified email at unt.edu
Saraju P. MohantyProfessor, University of North TexasVerified email at unt.edu
Nagarajan RanganathanDistinguished University Professor Emeritus of Computer Science, University of South FloridaVerified email at cse.usf.edu
Prabhat MishraProfessor, Univ. of Florida, IEEE Fellow, AAAS Fellow, ACM Distinguished MemberVerified email at ufl.edu
Kanad Basu (কণাদ বসু)University of Texas at DallasVerified email at utdallas.edu
Jimson MathewIIT patnaVerified email at iitp.ac.in
Dhruva GhaiProfessor, Oriental University, Indore, IndiaVerified email at orientaluniversity.in
Sharad MalikProfessor of Electrical and Computer Engineering, Princeton UniversityVerified email at princeton.edu
Dr. Bijoy A. JoseAssociate Professor, Department of Computer Science, Cochin University of Science and TechnologyVerified email at cusat.ac.in
Li-Shiuan PehProfessor of Computer Science, National University of SingaporeVerified email at nus.edu.sg
Bin LiIntelVerified email at intel.com
Oleg GaritselovGraduate Reesearch Assistant, University of North TexasVerified email at unt.edu
Om PatraStudent at School of Computer Science & Engineering, Xavier UniversityVerified email at stu.xub.edu.in
Dr. Bhaskar MondalAssistant Professor of Computer Science, National Institute of Technology PatnaVerified email at nitp.ac.in
Stas PolonskySamsung R&D Institute RussiaVerified email at samsung.com
Chris ChuIowa State UniversityVerified email at iastate.edu
Dhiraj K PradhanProfessor of Computer Science, University of BristolVerified email at cs.bris.ac.uk
Amir NahirAppleVerified email at apple.com
Preeti Ranjan PandaProfessor in Computer Science and Engineering, Indian Institute of Technology DelhiVerified email at cse.iitd.ac.in
Dr. Monalisa MandalDepartment of Computer Science & Engineering, National Institute of Technology, DurgapurVerified email at cse.nitdgp.ac.in

Prof. (Dr.) Priyadarsan Patra

Vice-Chancellor, NIST University

Verified email at seedsnet.org - Homepage

Architecture Machine Learning & AI System Validation and Debug Lowpower Circuits Systems and


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Low-power High-level Synthesis for Nanoscale CMOS Circuits SP Mohanty, N Ranganathan, E Kougianos, P Patra Springer, ISBN: 978-0-387-76474-0, 2008	124	2008
On the cusp of a validation wall P Patra IEEE Design & Test of Computers 24 (2), 193-196, 2007	119	2007
Impact of process and temperature variations on network-on-chip design exploration B Li, LS Peh, P Patra Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008), 117-126, 2008	89	2008
A design for digital, dynamic clock deskew CE Dike, NA Kurd, P Patra, J Barkatullah 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No …, 2003	58	2003
Runtime validation of memory ordering using constraint graph checking K Chen, S Malik, P Patra 2008 IEEE 14th International Symposium on High Performance Computer …, 2008	53	2008
A course recommendation system based on grades B Mondal, O Patra, S Mishra, P Patra IEEE, 2019	52	2019
Test, validation, and debug architecture MB Trobough, KK Tiruvallur, CB Prudvi, CE Iovin, DW Grawrock, ... US Patent 10,198,333, 2019	42	2019
Efficient combination of trace and scan signals for post silicon validation and debug K Basu, P Mishra, P Patra 2011 IEEE International Test Conference, 1-8, 2011	41	2011
Efficient building blocks for delay insensitive circuits P Patra, DS Fussell Proceedings of 1994 IEEE Symposium on Advanced Research in Asynchronous …, 1994	41	1994
Delay insensitive logic for RSFQ superconductor technology P Patra, S Polonsky, DS Fussell Proceedings Third International Symposium on Advanced Research in …, 1997	34	1997
Noise and power optimization in high performance circuits P Patra, B Chappell US Patent App. US 09/964,803, 2001	30	2001
On efficient adiabatic design of MOS circuits P Patra, D Fussell Workshop on Physics and Computation, Boston, 260-269, 1996	28	1996
Automated phase assignment for the synthesis of low power domino circuits P Patra, U Narayanan Proceedings of the 36th annual ACM/IEEE Design Automation Conference, 379-384, 1999	27	1999
A novel performance-driven topology design algorithm M Pan, C Chu, P Patra 2007 Asia and South Pacific Design Automation Conference, 244-249, 2007	26	2007
Conservative delay-insensitive circuits P Patra, DS Fussell Workshop on Physics and Computation, 248-259, 1996	26	1996
Approaches to design of circuits for low-power computation P Patra The University of Texas at Austin, 1995	26	1995
Dynamic selection of trace signals for post-silicon debug K Basu, P Mishra, P Patra, A Nahir, A Adir 2013 14th International Workshop on Microprocessor Test and Verification, 62-67, 2013	25	2013
Building-blocks for designing DI circuits P Patra, DS Fussell University of Texas at Austin, Department of Computer Sciences, 1993	21	1993
Power consumption reduction for domino circuits P Patra, UK Narayanan US Patent 6,529,861, 2003	19	2003
Nano-cmos mixed-signal circuit metamodeling techniques: A comparative study O Garitselov, SP Mohanty, E Kougianos, P Patra 2010 International Symposium on Electronic System Design, 191-196, 2010	16	2010

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