Ganesh Bikshandi
Ganesh Bikshandi
Mathworks USA
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Cited by
Cited by
Programming for parallelism and locality with hierarchically tiled arrays
G Bikshandi, J Guo, D Hoeflinger, G Almasi, BB Fraguela, MJ Garzarán, ...
Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice …, 2006
The asynchronous partitioned global address space model
V Saraswat, G Almasi, G Bikshandi, C Cascaval, D Cunningham, D Grove, ...
The First Workshop on Advances in Message Passing, 1-8, 2010
Programming with tiles
J Guo, G Bikshandi, BB Fraguela, MJ Garzaran, D Padua
Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of …, 2008
Tera-scale 1D FFT with low-communication algorithm and Intel® Xeon Phi™ coprocessors
J Park, G Bikshandi, K Vaidyanathan, PTP Tang, P Dubey, D Kim
Proceedings of the International Conference on High Performance Computing …, 2013
The hierarchically tiled arrays programming approach
BB Fraguela, J Guo, G Bikshandi, MJ Garzaran, G Almasi, J Moreira, ...
Proceedings of the 7th workshop on Workshop on languages, compilers, and run …, 2004
Efficient, portable implementation of asynchronous multi-place programs
G Bikshandi, JG Castanos, SB Kodali, VK Nandivada, I Peshansky, ...
ACM Sigplan Notices 44 (4), 271-282, 2009
Writing productive stencil codes with overlapped tiling
J Guo, G Bikshandi, BB Fraguela, D Padua
Concurrency and Computation: Practice and Experience 21 (1), 25-39, 2009
Optimization techniques for efficient HTA programs
BB Fraguela, G Bikshandi, J Guo, MJ Garzarán, D Padua, C Von Praun
Parallel Computing 38 (9), 465-484, 2012
Design and use of htalib–a library for hierarchically tiled arrays
G Bikshandi, J Guo, C Von Praun, G Tanase, BB Fraguela, MJ Garzarán, ...
International Workshop on Languages and Compilers for Parallel Computing, 17-32, 2006
Object liveness tracking for use in processing device cache
CJ Hughes, D Kim, JS Park, RM Yoo, G Bikshandi
US Patent 9,740,623, 2017
Hierarchically tiled arrays for parallelism and locality
J Guo, G Bikshandi, D Hoeflinger, G Almasi, B Fraguela, MJ Garzarán, ...
Proceedings 20th IEEE International Parallel & Distributed Processing …, 2006
Compiler optimization for complex exponential calculations
G Bikshandi, D Kim
US Patent 9,372,678, 2016
Parallel Programming with hierarchically tiled arrays
G Bikshandi
Systems and methods for automatically optimizing high performance computing programming languages
G Bikshandi, KN Venkata, I Peshansky, VA Saraswat
US Patent 8,924,946, 2014
Implementation of parallel numerical algorithms using hierarchically tiled arrays
G Bikshandi, BB Fraguela, J Guo, MJ Garzarán, G Almási, J Moreira, ...
Languages and Compilers for High Performance Computing: 17th International …, 2005
A comparative study and empirical evaluation of global view high performance Linpack program in X10
G Bikshandi, G Almasi, S Kodali, I Peshansky, V Saraswat, S Sur
Proceedings of the Third Conference on Partitioned Global Address Space …, 2009
Accelerating generic loop iterators using speculative execution
G Bikshandi, D Das, SR Sarangi
US Patent 8,701,099, 2014
Design and Usage of htalib–a C++ Library for Hierarchically Tiled Arrays
G Bikshandi, J Guo, C von Praun, G Tanase, BB Fraguela, MJ Garzaran, ...
DefensiveDriving: Guarding Operating System from Device Driver Bugs and Crashes
G Bikshandi, J Guo, J Trobec
A comparative study and empirical evaluation of global view HPL program in X10
G Bikshandi, G Almasi, S Kodali, V Saraswat, S Sur
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