| Towards collaborative intelligent IoT eHealth: From device to fog, and cloud B Farahani, M Barzegari, FS Aliee, KA Shaik Microprocessors and Microsystems 72, 102938, 2020 | 110 | 2020 |
| SRAM with Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes S. Salahuddin, K.A. Shaik, et.al. IEEE Electron Device Letters 40 (8), 1261-1264, 2019 | 34 | 2019 |
| Backside power delivery as a scaling knob for future systems B Chava, KA Shaik, A Jourdain, S Guissi, P Weckx, J Ryckaert, ... Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 14 | 2019 |
| Static random access memory K Itoh, A Amara, KA Shaik US Patent 10,141,047, 2018 | 12 | 2018 |
| Design of low power and high speed comparator with sub-32-nm Double Gate-MOSFET VR Bhumireddy, KA Shaik, A Amara, S Sen, CD Parikh, D Nagchoudhuri, ... 2013 IEEE International Conference on Circuits and Systems (ICCAS), 1-4, 2013 | 11 | 2013 |
| Ge Devices: A Potential Candidate for Sub-5-nm Nodes? N. Sharan, K. A. Shaik, et. al. IEEE Transactions on Electron Devices 66 (11), 4997-5002, 2019 | 10 | 2019 |
| Low power and fast adder implementation with Double Gate MOSFETs KA Shaik, A Amara, CD Parikh, A Singhal 2011 Faible Tension Faible Consommation (FTFC), 23-26, 2011 | 4 | 2011 |
| 0.5-V sub-ns open-BL SRAM array with mid-point-sensing multi-power 5T cell K Itoh, KA Shaik, A Amara 2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2892-2895, 2015 | 3 | 2015 |
| Compute-in-memory (CIM) employing low-power CIM circuits employing static random access memory (SRAM) bit cells, particularly for multiply-and-accumluate (MAC) operations KA Shaik, B Chava, DS Pathan US Patent 11,176,991, 2021 | 2 | 2021 |
| Optimization of read and write performance of SRAMs for node 5nm and beyond KA Shaik, M Gupta, P Weckx, A Spessot Design-Process-Technology Co-optimization for Manufacturability XIII 10962 …, 2019 | 2 | 2019 |
| A distortion reduction technique for bootstrapped-gate MOS Sample-and-Hold circuits using body-effect compensation S Sen, KA Shaik, J Mukherjee, P Dhalvaniya 2014 IEEE Faible Tension Faible Consommation, 1-4, 2014 | 2 | 2014 |
| Folded series switches TH Williams, C Roche, KA Shaik, H Lee, RL Mills, B Griffitts US Patent App. 17/939,392, 2024 | | 2024 |
| Memory bit cell circuit including a bit line coupled to a static random-access memory (SRAM) bit cell circuit and a non-volatile memory (NVM) bit cell circuit and a memory bit … KA Shaik, B Chava US Patent 11,749,327, 2023 | | 2023 |
| Packed terminal transistors TH Williams, KA Shaik, P JeongAh, R Thomas, H Siddaiah, R Kumar US Patent App. 17/651,561, 2023 | | 2023 |
| Control circuit for a line of a memory array J Louche, O Mercier, KA Shaik US Patent App. 15/866,156, 2018 | | 2018 |
| 0.5-V 50-mV-swing 1.2-GHz 28-nm-FD-SOI 32-bit dynamic bus architecture with dummy bus KA Shaik, K Itoh, A Amara 2016 17th International Symposium on Quality Electronic Design (ISQED), 380-385, 2016 | | 2016 |
| High-speed low-power 0.5-V 28-nm FD-SOI 5T-cell SRAMs K Shaik Paris 6, 2016 | | 2016 |
| 0.5-V Sub-ns Open-BL SRAM Array with Mid-Point-Sensing Multi-Power-Supply 5T Cell KA Shaik, K Itoh, A Amara IEICE Transactions on Fundamentals of Electronics, Communications and …, 2016 | | 2016 |
| 0.5-V 350-ps 28-nm FD-SOI SRAM array with dynamic power-supply 5T cell KA Shaik, K Itoh, A Amara 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015 | | 2015 |
| Energy efficiency optimization for digital applications in 28nm UTBB FDSOI technology A Amara, N Gupta, KA Shaik, C Anghel, K Itoh 2015 22nd International Conference Mixed Design of Integrated Circuits …, 2015 | | 2015 |
Amara AmaraProfessor, Director of Research, ISEP ParisVerified email at isep.fr
