| STATICA: A 512-spin 0.25 M-weight annealing processor with an all-spin-updates-at-once architecture for combinatorial optimization with complete spin–spin interactions K Yamamoto, K Kawamura, K Ando, N Mertig, T Takemoto, M Yamaoka, ... IEEE Journal of Solid-State Circuits 56 (1), 165-178, 2020 | 89 | 2020 |
| Amorphica: 4-replica 512 fully connected spin 336MHz metamorphic annealer with programmable optimization strategy and compressed-spin-transfer multi-chip extension K Kawamura, J Yu, D Okonogi, S Jimbo, G Inoue, A Hyodo, ... 2023 IEEE International Solid-State Circuits Conference (ISSCC), 42-44, 2023 | 27 | 2023 |
| A loop structure optimization targeting high-level synthesis of fast number theoretic transform K Kawamura, M Yanagisawa, N Togawa 2018 19th International Symposium on Quality Electronic Design (ISQED), 106-111, 2018 | 26 | 2018 |
| Hiddenite: 4K-PE hidden network inference 4D-tensor engine exploiting on-chip model construction achieving 34.8-to-16.0 TOPS/W for CIFAR-100 and ImageNet K Hirose, J Yu, K Ando, Y Okoshi, ÁL García-Arias, J Suzuki, T Van Chu, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 24 | 2022 |
| Implementation of a ROS-based autonomous vehicle on an FPGA board K Hasegawa, K Takasaki, M Nishizawa, R Ishikawa, K Kawamura, ... 2019 International Conference on Field-Programmable Technology (ICFPT), 457-460, 2019 | 20 | 2019 |
| Mixing time and simulated annealing for the stochastic cellular automata BH Fukushima-Kimura, S Handa, K Kamakura, Y Kamijima, K Kawamura, ... Journal of Statistical Physics 190 (4), 79, 2023 | 12 | 2023 |
| Mapping constrained slot-placement problems to Ising models and its evaluations by an Ising machine S Kanamaru, K Kawamura, S Tanaka, Y Tomita, H Matsuoka, ... 2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin …, 2019 | 11 | 2019 |
| A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration K Fujiwara, K Kawamura, M Yanagisawa, N Togawa 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 1-4, 2016 | 9 | 2016 |
| Multicoated Supermasks Enhance Hidden Networks. Y Okoshi, ÁL García-Arias, K Hirose, K Ando, K Kawamura, T Van Chu, ... ICML, 17045-17055, 2022 | 8 | 2022 |
| Clock skew estimate modeling for FPGA high-level synthesis and its application K Fujiwara, K Kawamura, M Yanagisawa, N Togawa 2015 IEEE 11th International Conference on ASIC (ASICON), 1-4, 2015 | 8 | 2015 |
| A high-performance and flexible fpga inference accelerator for decision forests based on prior feature space partitioning T Van Chu, R Kitajima, K Kawamura, J Yu, M Motomura 2021 International Conference on Field-Programmable Technology (ICFPT), 1-10, 2021 | 6 | 2021 |
| Solving constrained slot placement problems using an Ising machine and its evaluations S Kanamaru, K Kawamura, S Tanaka, Y Tomita, N Togawa IEICE TRANSACTIONS on Information and Systems 104 (2), 226-236, 2021 | 6 | 2021 |
| Multicoated and Folded Graph Neural Networks with Strong Lottery Tickets J Yan, H Ito, ÁL García-Arias, Y Okoshi, H Otsuka, K Kawamura, ... Learning on Graphs Conference, 11: 1-11: 18, 2024 | 3 | 2024 |
| Pianissimo: A Sub-mW Class DNN Accelerator with Progressive Bit-by-Bit Datapath Architecture for Adaptive Inference at Edge J Suzuki, J Yu, M Yasunaga, ÁL García-Arias, Y Okoshi, S Kumazawa, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 3 | 2023 |
| A hybrid integer encoding method for obtaining high-quality solutions of quadratic knapsack problems on solid-state annealers S Jimbo, D Okonogi, K Ando, T Van Chu, J Yu, M Motomura, K Kawamura IEICE TRANSACTIONS on Information and Systems 105 (12), 2019-2031, 2022 | 3 | 2022 |
| Stochastic optimization via parallel dynamics: rigorous results and simulations BH Fukushima-Kimura, Y Kamijima, K Kawamura, A Sakai Proceedings of the ISCIE International Symposium on Stochastic Systems …, 2022 | 3 | 2022 |
| Interconnection-delay and clock-skew estimate modelings for floorplan-driven high-level synthesis targeting FPGA designs K Fujiwara, K Kawamura, M Yanagisawa, N Togawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2016 | 3 | 2016 |
| A floorplan-driven high-level synthesis algorithm for multiplexer reduction targeting fpga designs K Fujiwara, K Kawamura, S Abe, M Yanagisawa, N Togawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2015 | 3 | 2015 |
| A floorplan-aware high-level synthesis algorithm for multiplexer reduction targeting FPGA designs K Fujiwara, S Abe, K Kawamura, M Yanagisawa, N Togawa 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 244-247, 2014 | 3 | 2014 |
| A thermal-aware high-level synthesis algorithm for RDR architectures through binding and allocation K Kawamura, M Yanagisawa, N Togawa IEICE Transactions on Fundamentals of Electronics, Communications and …, 2013 | 3 | 2013 |
