| A hardware–software blueprint for flexible deep learning specialization T Moreau, T Chen, L Vega, J Roesch, E Yan, L Zheng, J Fromm, Z Jiang, ... IEEE Micro 39 (5), 8-16, 2019 | 188 | 2019 |
| Asic clouds: Specializing the datacenter I Magaki, M Khazraee, LV Gutierrez, MB Taylor ACM SIGARCH Computer Architecture News 44 (3), 178-190, 2016 | 155 | 2016 |
| The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ... IEEE Micro 38 (2), 30-41, 2018 | 130 | 2018 |
| Moonwalk: Nre optimization in asic clouds M Khazraee, L Zhang, L Vega, MB Taylor ACM SIGARCH Computer Architecture News 45 (1), 511-526, 2017 | 80 | 2017 |
| Celerity: An Open-Source RISC-V Tiered Accelerator Fabric T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ... Symp. on High Performance Chips (Hot Chips), 2017 | 38 | 2017 |
| A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With Mesh On-Chip Network and an All-Digital Synthesized PLL in 16nm CMOS A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... 2019 Symposium on VLSI Circuits, C30-C31, 2019 | 34 | 2019 |
| Extreme datacenter specialization for planet-scale computing: Asic clouds S Xie, S Davidson, I Magaki, M Khazraee, L Vega, L Zhang, MB Taylor ACM SIGOPS Operating Systems Review 52 (1), 96-108, 2018 | 33 | 2018 |
| Evaluating Celerity: A 16-nm 695 Giga-RISC-V Instructions/s Manycore Processor With Synthesizable PLL A Rovinski, C Zhao, K Al-Hawaj, P Gao, S Xie, C Torng, S Davidson, ... IEEE Solid-State Circuits Letters 2 (12), 289-292, 2019 | 31 | 2019 |
| Relay: A high-level compiler for deep learning J Roesch, S Lyubomirsky, M Kirisame, L Weber, J Pollock, L Vega, ... arXiv preprint arXiv:1904.08368, 2019 | 28 | 2019 |
| Specializing a Planet's Computation: ASIC Clouds M Khazraee, LV Gutierrez, I Magaki, MB Taylor IEEE Micro 37 (3), 62-69, 2017 | 28 | 2017 |
| Asic clouds: Specializing the datacenter for planet-scale applications MB Taylor, L Vega, M Khazraee, I Magaki, S Davidson, D Richmond Communications of the ACM 63 (7), 103-109, 2020 | 27 | 2020 |
| Hiding intermittent information leakage with architectural support for blinking A Althoff, J McMahan, L Vega, S Davidson, T Sherwood, M Taylor, ... 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018 | 27 | 2018 |
| Power Side Channels in Security ICs: Hardware Countermeasures L Zhang, L Vega, M Taylor arXiv preprint arXiv:1605.00681, 2016 | 24 | 2016 |
| Experiences Using the RISC-V Ecosystem to Design an Accelerator-Centric SoC in TSMC 16nm TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ... 1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017 | 16 | 2017 |
| Reticle: a virtual machine for programming modern FPGAs L Vega, J McMahan, A Sampson, D Grossman, L Ceze Proceedings of the 42nd ACM SIGPLAN International Conference on Programming …, 2021 | 12 | 2021 |
| RV-IOV: Tethering RISC-V Processors via Scalable I/O Virtualization L Vega, M Taylor Workshop on Computer Architecture Research with RISC-V (CARRV), 2017 | 11 | 2017 |
| LastLayer: Toward Hardware and Software Continuous Integration L Vega, J Roesch, J McMahan, L Ceze IEEE Micro 40 (4), 103-111, 2020 | 3 | 2020 |
| Programming Abstractions and Efficient Compilation Techniques for Modern FPGA L Vega University of Washington, 2022 | | 2022 |
| Journal: ACM SIGARCH Computer Architecture News, 2017, № 1, p. 511-526 M Khazraee, L Zhang, L Vega, MB Taylor ACM SIGARCH Computer Architecture News, 511-526, 2017 | | 2017 |
| AXI4-Stream Upsizing/Downsizing Data Width Converters for Hardware-In-the-Loop Simulations L Vega, P Schläfer, C de Schryver | | 2013 |
Michael TaylorProfessor of Computer Science & Engineering and EE, U. WashingtonVerified email at uw.edu
