| Online BIST for embedded systems H Al-Asaad, BT Murray, JP Hayes IEEE design & Test of Computers 15 (4), 17-24, 1998 | 119 | 1998 |
| Design verification via simulation and automatic test pattern generation H Al-Asaad, JP Hayes Proceedings of IEEE International Conference on Computer Aided Design (ICCAD …, 1995 | 64 | 1995 |
| High-level design verification of microprocessors via error modeling DV Campenhout, H Al-Asaad, JP Hayes, T Mudge, RB Brown ACM Transactions on Design Automation of Electronic Systems (TODAES) 3 (4 …, 1998 | 59 | 1998 |
| Automatically generating an input sequence for a circuit design using mutant-based verification J Campos, H Al-Asaad US Patent 7,694,253, 2010 | 35 | 2010 |
| On-line built-in self-test for operational faults H Al-Asaad, M Shringi 2000 IEEE Autotestcon Proceedings. IEEE Systems Readiness Technology …, 2000 | 30 | 2000 |
| Scalable test generators for high-speed datapath circuits H Al-Asaad, JP Hayes, BT Murray Journal of Electronic Testing 12, 111-125, 1998 | 28 | 1998 |
| Simulation-based approximate global fault collapsing H Al-Assad, R Lee Proc. International Conf. on VLSI, 72-77, 2002 | 26 | 2002 |
| A new low power high performance flip-flop A Sayed, H Al-Asaad 2006 49th IEEE International Midwest Symposium on Circuits and Systems 1 …, 2006 | 18 | 2006 |
| Logic design validation via simulation and automatic test pattern generation H Al-Asaad, JP Hayes Journal of Electronic Testing 16 (6), 575-589, 2000 | 18 | 2000 |
| ESIM: A multimodel design error and fault simulator for logic circuits H Al-Asaad, JP Hayes Proceedings 18th IEEE VLSI Test Symposium, 221-228, 2000 | 11 | 2000 |
| Overview of assertion-based verification and its applications Z Ren, H Al-Asaad Int’l Conf. Embedded Systems, Cyber-physical Systems, & Applications, 2016 | 10 | 2016 |
| Non-concurrent on-line testing via scan chains H Al-Asaad, P Moore 2006 IEEE Autotestcon, 683-689, 2006 | 10 | 2006 |
| Survey and Evaluation of Low-Power Full-Adder Cells. A Sayed, H Al-Asaad ESA/VLSI, 332-338, 2004 | 10 | 2004 |
| Lifetime validation of digital systems via fault modeling and test generation HS Al-Asaad University of Michigan, 1998 | 10 | 1998 |
| High-level design verification of microprocessors via error modeling H Al-Asaad, D Van Campenhout, JP Hayes, T Mudge, RB Brown IEEE International High-Level Design Validation and Test Workshop, 194-201, 1997 | 10 | 1997 |
| Low-Power Flip-Flops: Survey, Comparative Evaluation, and a New Design A Sayed, H Al-Asaad International Journal of Engineering and Technology 3 (3), 279, 2011 | 9 | 2011 |
| Efficient techniques for reducing error latency in on-line periodic built-in self-test H Al-Asaad IEEE instrumentation & measurement magazine 13 (4), 28-32, 2010 | 9 | 2010 |
| Survey and Evaluation of Low-Power Flip-Flops. A Sayed, H Al-Asaad CDES, 77-83, 2006 | 9 | 2006 |
| Mutation-based validation of high-level microprocessor implementations J Campos, H Al-Asaad Proceedings. Ninth IEEE International High-Level Design Validation and Test …, 2004 | 9 | 2004 |
| Soft error detection via double execution with hardware assistance L Bustamante, H Al-Asaad 2012 IEEE AUTOTESTCON Proceedings, 291-293, 2012 | 8 | 2012 |
Trevor MudgeBredt Family Professor of Engineering, University of MichiganVerified email at eecs.umich.edu
