| A short-channel common double-gate MOSFET model adapted to gate oxide thickness asymmetry N Sharan, S Mahapatra IEEE Transactions on Electron Devices 61 (8), 2732-2737, 2014 | 15 | 2014 |
| Ge devices: A potential candidate for sub-5-nm nodes? N Sharan, KA Shaik, D Jang, P Schuddinck, D Yakimets, MG Bardon, ... IEEE Transactions on Electron Devices 66 (11), 4997-5002, 2019 | 10 | 2019 |
| Nonquasi-static charge model for common double-gate MOSFETs adapted to gate oxide thickness asymmetry N Sharan, S Mahapatra IEEE transactions on electron devices 60 (7), 2419-2422, 2013 | 9 | 2013 |
| Impact of strain and channel thickness on performance of biaxial strained silicon MOSFETs N Sharan, AK Rana International Journal of VLSI Design & Communication Systems 2 (1), 61-71, 2011 | 8 | 2011 |
| Experimental validation of process-induced variability aware SPICE simulation platform for sub-20 nm FinFET technologies A Rawat, N Sharan, D Jang, T Chiarella, FM Bufler, F Catthoor, B Parvais, ... IEEE Transactions on Electron Devices 68 (3), 976-980, 2021 | 6 | 2021 |
| Cost effective FinFET platform for stand alone DRAM 1Y and beyond memory periphery A Spessot, N Sharan, H Oh, R Ritzenthaler, ED Litta, B O'Sullivan, ... 2018 IEEE International Memory Workshop (IMW), 1-4, 2018 | 5 | 2018 |
| Compact noise modelling for common double‐gate metal–oxide–semiconductor field‐effect transistor adapted to gate‐oxide‐thickness asymmetry N Sharan, S Mahapatra IET Circuits, Devices & Systems 10 (1), 62-67, 2016 | 5 | 2016 |
| Design and Performance Comparison of CNTFET-Based Binary and Ternary Logic Inverter and Decoder With 32 nm CMOS Technology M Khandelwal, N Sharan Advances in Computer and Computational Sciences: Proceedings of ICCCCS 2016 …, 2017 | 3 | 2017 |
| Characterization of 6T CMOS SRAM in 90nm technology for various leakage reduction techniques A Chauhan, DS Chauhan, N Sharan 2016 IEEE Students' Conference on Electrical, Electronics and Computer …, 2016 | 2 | 2016 |
| Continuity equation based nonquasi-static charge model for independent double gate MOSFET N Sharan, S Mahapatra Journal of Computational Electronics 13, 353-359, 2014 | 2 | 2014 |
| Compact Modeling of Short Channel Common Double Gate MOSFET Adapted to Gate-Oxide Thickness Asymmetry N Sharan | | 2018 |
| Device challenges for logic scaling for sub-5 nm node D Jang, M Garcia Bardon, D Yakimets, P Schuddinck, LA Ragnarsson, ... | | 2018 |
| Reliable techniques of leakage current reduction for SRAM-6T Cell: A review A Chauhan, DS Chauhan, N Sharan 2016 3rd International Conference on Computing for Sustainable Global …, 2016 | | 2016 |
| indDG: A new compact model for common double gate MOSFET adapted to gate oxide thickness asymmetry C Kumar, N Sharan, S Mahapatra 2015 IEEE International Conference on Electronics, Computing and …, 2015 | | 2015 |
| Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness Asymmetry N Sharan, S Mahapatra 2014 27th International Conference on VLSI Design and 2014 13th …, 2014 | | 2014 |
| Analysis of uniaxial strained silicon MOSFETs performance NSA Rana Innovative Conference on Embedded System, Mobile Communication and Computing, 2011 | | 2011 |
| Analysis of VLSI Circuits Designed with Single and Dual Channel Strained Silicon MOSFETs in Nanoregime N Sharan, A Rana Journal of VLSI Design Tools & Technology 1 (1), 2011 | | 2011 |
| Performance Evaluation of Strained Channel NMOS in nanoregime NSA Rana International Journal of Micro & Nano Systems 2 (1), 53-58, 2011 | | 2011 |
| NQS Modeling of independent DG MOSFET using RTA Approach N Sharan, S Mahapatra | | |
