Method of forming a metal gate in a semiconductor device using atomic layer deposition process DG Park, HJ Cho, KY Lim US Patent 7,157,359, 2007 | 193 | 2007 |
Method of manufacturing semiconductor devices T Cha, H Cho, S Jang, TK Kim, KY Lim, D Park, J Park, IS Yeo | 162* | 2001 |
Characteristics of n {sup+} polycrystalline-Si/Al {sub 2} O {sub 3}/Si metal {endash} oxide {endash} semiconductor structures prepared by atomic layer chemical vapor deposition … DG Park, HJ Cho, KY Lim, C Lim, IS Yeo, JS Roh, JW Park Journal of Applied Physics 89 (11), 2001 | 139 | 2001 |
Adhesion and interface chemical reactions of Cu/polyimide and Cu/TiN by XPS WJ Lee, YS Lee, SK Rha, YJ Lee, KY Lim, YD Chung, CN Whang Applied Surface Science 205 (1), 128-136, 2003 | 115 | 2003 |
Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products R Xie, KY Lim, MG Sung, RRH Kim US Patent 9,412,616, 2016 | 110 | 2016 |
Method of manufacturing semiconductor devices with titanium aluminum nitride work function DG Park, TH Cha, SA Jang, HJ Cho, TK Kim, KY Lim, IS Yeo, JW Park US Patent 6,506,676, 2003 | 105 | 2003 |
Characteristics of n+ polycrystalline-Si/Al 2 O 3/Si metal–oxide–semiconductor structures prepared by atomic layer chemical vapor deposition using Al (CH 3) 3 and H 2 O vapor DG Park, HJ Cho, KY Lim, C Lim, IS Yeo, JS Roh, JW Park Journal of Applied Physics 89 (11), 6275-6280, 2001 | 101 | 2001 |
Methods of forming vertical transistor devices with self-aligned top source/drain conductive contacts JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim US Patent 9,530,866, 2016 | 93 | 2016 |
METHOD FOR FABRICATING SEMICONDUCTOR MEMORY DEVICE LIM Kwan-Yong, S Min-Gyu, CHO Heung-Jae US Patent App. 13/170,662, 2011 | 83* | 2011 |
Charge redistribution and electronic behavior in Pd-Au alloys YS Lee, Y Jeon, YD Chung, KY Lim, CN Whang, SJ Oh JOURNAL-KOREAN PHYSICAL SOCIETY 37 (4), 451-455, 2000 | 83 | 2000 |
Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products R Xie, MG Sung, RRH Kim, KY Lim, C Park US Patent 9,362,181, 2016 | 80 | 2016 |
Novel stress-memorization-technology (SMT) for high electron mobility enhancement of gate last high-k/metal gate devices KY Lim, H Lee, C Ryu, KI Seo, U Kwon, S Kim, J Choi, K Oh, HK Jeon, ... Electron Devices Meeting (IEDM), 2010 IEEE International, 10.1. 1-10.1. 4, 2010 | 68 | 2010 |
FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... VLSI Symposium on Technology, 2016 | 66 | 2016 |
Impact of atomic-layer-deposited TiN on the gate oxide quality of W/TiN/SiO 2/Si metal–oxide–semiconductor structures DG Park, KY Lim, HJ Cho, TH Cha, IS Yeo, JS Roh, JW Park Applied physics letters 80 (14), 2514-2516, 2002 | 66 | 2002 |
Robust ternary metal gate electrodes for dual gate CMOS devices DG Park, TH Cha, KY Lim, HJ Cho, TK Kim, SA Jang, YS Suh, V Misra, ... Electron Devices Meeting, 2001. IEDM'01. Technical Digest. International, 30 …, 2001 | 66 | 2001 |
Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device SJ Bentley, JH Zhang, KY Lim, H Niimi US Patent 9,640,636, 2017 | 62 | 2017 |
XPS core‐level shifts and XANES studies of Cu–Pt and Co–Pt alloys YS Lee, KY Lim, YD Chung, CN Whang, Y Jeon Surface and interface analysis 30 (1), 475-478, 2000 | 60 | 2000 |
Self-aligned gate-first VFETs using a gate spacer recess JH Zhang, KY Lim, SJ Bentley, C Park US Patent 9,536,793, 2017 | 59 | 2017 |
Electrical characteristics and thermal stability of n+ polycrystalline-Si/ZrO 2/SiO 2/Si metal–oxide–semiconductor capacitors KY Lim, DG Park, HJ Cho, JJ Kim, JM Yang, IIS Choi, IS Yeo, JW Park Journal of applied physics 91 (1), 414-419, 2002 | 55 | 2002 |
Methods of forming vertical transistor devices with self-aligned replacement gate structures JH Zhang, C Radens, SJ Bentley, BA Cohen, KY Lim US Patent 9,530,863, 2016 | 50 | 2016 |